Publications

Daněk, L., & Novotný, M. (2024, August). How Primitive but How Effective: Fault-Injection Attack on Cryptographic Accelerator of Microchip CEC 1702 Microcontroller. In 2024 27th Euromicro Conference on Digital System Design (DSD) (pp. 129-136). IEEE Computer Soc. [doi] [pdf]

Olekšák, M., & Miškovský, V. (2024, August). Impact of Compiler Optimization Flags on Side-Channel Information Leakage of SipHash algorithm. In 2024 27th Euromicro Conference on Digital System Design (DSD) (pp. 51-56). IEEE Computer Soc. [doi] [pdf]

Horníčková, T., Přeučil, T., Novotný, M. & Martinásek, Z. (2023, June). Side-Channel Analysis of Cryptographic Processor CEC 1702. In 2023 12th Mediterranean Conference on Embedded Computing (MECO) (pp. 178-181). IEEE. [doi] [pdf]

Olekšák, M., & Miškovský, V. (2023, June). Is ASCON the best choice regarding the Side-channel Analysis? In 2023 12th Mediterranean Conference on Embedded Computing (MECO) (pp. 173-177). IEEE. [doi] [pdf]

Pokorný, D., Novotný, M. (2023, June). Introduction to Probing Security. In Proceedings of the 11th Prague Embedded Systems Workshop (p. 9). CTU FIT, Department of Digital Design.

Pokorný, D., Socha, P., Novotný, M. (2023, July). Equivalent Keys as a Side-Channel Countermeasure for the Rainbow Signature Scheme. In Proceedings of the 11th Prague Embedded Systems Workshop (p. 34). CTU FIT, Department of Digital Design.

Přeučil, T., & Novotný, M. (2023, June). Surveying the security of access systems in Uppsala, Sweden. In 2023 12th Mediterranean Conference on Embedded Computing (MECO) (pp. 129-133). IEEE. [doi] [pdf]

Jedlicka, P., Malina, L., Socha, P., Gerlich, T., Martinasek, Z., & Hajny, J. (2022, August). On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography. In Proceedings of the 17th International Conference on Availability, Reliability and Security (pp. 1-9). [doi] [pdf]

Kálnai, P., & Havránek, M. Lazarus & BYOVD: Evil to the Windows Core. In 2022 VirusBulletin.

Mašek, V., & Novotný, M. (2022, April). Versatile Hardware Framework for Elliptic Curve Cryptography. In 2022 IEEE 25th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (pp. 80-83). IEEE. [doi] [pdf]

Olekšák, M., & Miškovský, V. (2022, April). Correlation Power Analysis of SipHash. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (pp. 84-87). IEEE. [doi] [pdf]

Pokorný, D., Socha, P., & Novotný, M. (2022). Equivalent Keys: Side-Channel Countermeasure for Post-Quantum Multivariate Quadratic Signatures. Electronics, 11, 3607. [doi] [pdf]

Přeučil, T., Socha, P., & Novotný, M. (2022, August). Implementation of the Rainbow signature scheme on SoC FPGA. In 2022 25th Euromicro Conference on Digital System Design (DSD) (pp. 513-519). IEEE Computer Soc. [doi] [pdf]

Socha, P., Miškovský, V., & Novotný, M. (2022). A Comprehensive Survey on the Non-Invasive Passive Side-Channel Analysis. Sensors, 22, 8096. [doi] [pdf]

Socha, P., Miškovský, V., & Novotný, M. (2022, June). A fair experimental evaluation of distance correlation side-channel distinguisher. In 2022 11th Mediterranean Conference on Embedded Computing (MECO) (pp. 110-113). IEEE. [doi] [pdf]

Balihar, T., & Novotný, M. (2021, June). Influence of Synthesis Parameters on Vulnerability to Side-Channel Attacks. In 2021 10th Mediterranean Conference on Embedded Computing (MECO) (pp. 735-740). IEEE. [doi] [pdf]

Klemsa J. (2021, July). Fast and Error-Free Negacyclic Integer Convolution Using Extended Fourier Transform. In 2021 Cyber Security Cryptography and Machine Learning (CSCML). (pp. 282-300). Springer, Cham. [doi] [pdf]

Klemsa, J. (2021). TFHE Parameter Setup for Effective and Error-Free Neural Network Prediction on Encrypted Data. In Intelligent Computing (pp. 702-721). Springer, Cham. [doi] [pdf]

Miškovský, V., Kubátová, H., & Novotný, M. (2021, September). Secure and dependable: Area-efficient masked and fault-tolerant architectures. In 2021 24th Euromicro Conference on Digital System Design (DSD) (pp. 333-338). IEEE Computer Soc. [doi] [pdf]

Pokorný, D., Socha, P., & Novotný, M. (2021, February). Side-channel attack on Rainbow post-quantum signature. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 565-568). IEEE. [doi] [pdf]

Socha, P., Miškovský, V., & Novotný, M. (2021). High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation. Microprocessors and Microsystems, 85, 104311. [doi]

Klemsa, J., & Novotný, M. (2020, July). Exploiting Linearity in White-Box AES with Differential Computation Analysis. In Science and Information Conference (pp. 404-419). Springer, Cham. [doi] [pdf]

Klemsa, J., & Novotný, M. (2020, June). WTFHE: neural-netWork-ready Torus Fully Homomorphic Encryption. In 2020 9th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-5). IEEE. [doi] [pdf]

Klemsa, J., & Trummová, I. (2020, February). Security Notions for the VeraGreg Framework and Their Reductions. In 2020 Third ISEA Conference on Security and Privacy (ISEA-ISAP) (pp. 8-20). IEEE. [doi] [pdf]

Moucha, P., Jeřábek, S., & Novotný, M. (2020, April). Novel Dummy Rounds Schemes as a DPA Countermeasure in PRESENT Cipher. In 2020 IEEE 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (pp. 1-4). IEEE. [doi] [pdf]

Moucha, P., Jeřábek, S., & Novotný, M. (2020, August). Novel Controller for Dummy Rounds Scheme DPA Countermeasure. In 2020 23rd Euromicro Conference on Digital System Design (DSD) (pp. 281-284). IEEE Computer Soc. [doi] [pdf]

Socha, P., & Novotný, M. (2020, August). Towards High-Level Synthesis of Polymorphic Side-Channel Countermeasures. In 2020 23rd Euromicro Conference on Digital System Design (DSD) (pp. 193-199). IEEE Computer Soc. [doi] [pdf]

Socha, P., Brejník, J., Balasch, J., Novotný, M., & Mentens, N. (2020). Side-channel countermeasures utilizing dynamic logic reconfiguration: Protecting AES/Rijndael and Serpent encryption in hardware. Microprocessors and Microsystems, 78, 103208. [doi]

Jeřábek, S., & Schmidt, J. (2019, April). Analyzing and Optimizing the Dummy Rounds Scheme. In 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (pp. 1-4). IEEE. [doi] [pdf]

Říha, J., Klemsa, J., & Novotný, M. (2019, June). Multiprecision ANSI C Library for Implementation of Cryptographic Algorithms on Microcontrollers. In 2019 8th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-4). IEEE. [doi] [pdf]

Socha, P., Brejník, J., Jeřábek, S., Novotný, M., & Mentens, N. (2019, August). Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent. In 2019 22nd Euromicro Conference on Digital System Design (DSD) (pp. 277-282). IEEE Computer Soc. [doi] [pdf]

Socha, P., Miškovský, V., & Novotný, M. (2019, June). First-Order and Higher-Order Power Analysis: Computational Approaches and Aspects. In 2019 8th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-5). IEEE. [doi] [pdf]

Socha, P., Miškovský, V., & Novotný, M. (2019, May) SICAK: An open-source SIde-Channel Analysis toolKit. In 2019 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE) [pdf]

Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2019). Efficient algorithmic evaluation of correlation power analysis: Key distinguisher based on the correlation trace derivative. Microprocessors and Microsystems, 71, 102858. [doi]

Jeřábek, S., Schmidt, J., Novotný, M., & Miškovský, V. (2018, August). Dummy rounds as a DPA countermeasure in hardware. In 2018 21st Euromicro Conference on Digital System Design (DSD) (pp. 523-528). IEEE. [doi] [pdf]

Klemsa, J., Kencl, L., & Vaněk, T. (2018, August). VeraGreg: A Framework for Verifiable Privacy-Preserving Data Aggregation. In 2018 17th IEEE International Conference On Trust, Security And Privacy In Computing And Communications/12th IEEE International Conference On Big Data Science And Engineering (TrustCom/BigDataSE) (pp. 1820-1825). IEEE. [doi] [pdf]

Mentens, N., Miskovsky, V., Novotny, M., & Vliegen, J. (2018). High-speed Side-channel-protected Encryption and Authentication in Hardware. Cryptology ePrint Archive. [pdf]

Miškovský, V., Kubátová, H., & Novotný, M. (2018, June). Speeding up differential power analysis using integrated power traces. In 2018 7th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-5). IEEE. [doi] [pdf]

Socha, P., Brejník, J., & Bartík, M. (2018, June). Attacking AES implementations using correlation power analysis on ZYBO Zynq-7000 SoC board. In 2018 7th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-4). IEEE. [doi] [pdf]

Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2018, August). Correlation Power Analysis Distinguisher Based on the Correlation Trace Derivative. In 2018 21st Euromicro Conference on Digital System Design (DSD) (pp. 565-568). IEEE Computer Soc. [doi] [pdf]

Buček, J., Novotný, M., & Štěpánek, F. (2017). Practical Session: Differential Power Analysis for Beginners. In Hardware Security and Trust (pp. 77-91). Springer, Cham. [doi] [pdf]

Jeřábek, S., Buček, J., Schmidt, J., & Novotný, M. (2017, June). Emulator of contactless smart cards in FPGA. In 2017 6th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-4). IEEE. [doi] [pdf]

Mazur, L., & Novotný, M. (2017, June). Differential power analysis on FPGA board: Boundaries of success. In 2017 6th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-4). IEEE. [doi] [pdf]

Miškovský, V., Kubátová, H., & Novotný, M. (2017). Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA. Microprocessors and Microsystems, 51, 220-226. [doi] [pdf]

Novotný, M. (2017). Cryptanalytic attacks on cyber-physical systems. Microprocessors and Microsystems, 52, 534-539. [doi] [pdf]

Říha, J., Miškovský, V., Kubátová, H., & Novotný, M. (2017, August). Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of Cryptographic Design. In 2017 Euromicro Conference on Digital System Design (DSD) (pp. 260-267). IEEE. [doi] [pdf]

Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2017, April). Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (pp. 184-189). IEEE. [doi] [pdf]

Miškovský, V., Kubátová, H., & Novotný, M. (2016, June). Influence of fault-tolerant design methods on differential power analysis resistance of AES cipher: Methodics and challenges. In 2016 5th Mediterranean Conference on Embedded Computing (MECO) (pp. 14-17). IEEE. [doi] [pdf]

Güneysu, T., Kasper, T., Novotný, M., Paar, C., Wienbrandt, L., & Zimmermann, R. (2013). High-performance cryptanalysis on RIVYERA and COPACOBANA computing systems. In High-Performance Computing Using FPGAs (pp. 335-366). Springer, New York, NY. [doi]

Štěpánek, F., Buček, J., & Novotný, M. (2013, September). Differential power analysis under constrained budget: Low cost education of hackers. In 2013 Euromicro Conference on Digital System Design (pp. 645-648). IEEE. [doi] [pdf]