Vojtěch Miškovský

Vojtěch Miškovský
Position
Assistant professor
Research Interests
Attack-resistant and fault-tolerant architectures
E-mail
vojtech.miskovsky@fit.cvut.cz
Room
A-1033
Address

Thákurova 2077/7
Praha

Biography

Vojtěch Miškovský is an assistant professor at Faculty of Information Technology at Czech Technical University in Prague, where he graduated in 2015 and defended his doctoral dissertation in 2020. His research interest is dependable and secure digital design.

Publications

2023

  • Olekšák, M., & Miškovský, V. (2023, June). Is ASCON the best choice regarding the Side-channel Analysis? In 2023 12th Mediterranean Conference on Embedded Computing (MECO) (pp. 173-177). IEEE. [doi] [pdf]

2022

  • Olekšák, M., & Miškovský, V. (2022, April). Correlation Power Analysis of SipHash. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (pp. 84-87). IEEE. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2022). A Comprehensive Survey on the Non-Invasive Passive Side-Channel Analysis. Sensors, 22, 8096. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2022, June). A fair experimental evaluation of distance correlation side-channel distinguisher. In 2022 11th Mediterranean Conference on Embedded Computing (MECO) (pp. 110-113). IEEE. [doi] [pdf]

2021

  • Miškovský, V., Kubátová, H., & Novotný, M. (2021, September). Secure and dependable: Area-efficient masked and fault-tolerant architectures. In 2021 24th Euromicro Conference on Digital System Design (DSD) (pp. 333-338). IEEE Computer Soc. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2021). High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation. Microprocessors and Microsystems, 85, 104311. [doi]

2019

  • Socha, P., Miškovský, V., & Novotný, M. (2019, June). First-Order and Higher-Order Power Analysis: Computational Approaches and Aspects. In 2019 8th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-5). IEEE. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2019, May) SICAK: An open-source SIde-Channel Analysis toolKit. In 2019 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE) [pdf]
  • Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2019). Efficient algorithmic evaluation of correlation power analysis: Key distinguisher based on the correlation trace derivative. Microprocessors and Microsystems, 71, 102858. [doi]

2018

  • Jeřábek, S., Schmidt, J., Novotný, M., & Miškovský, V. (2018, August). Dummy rounds as a DPA countermeasure in hardware. In 2018 21st Euromicro Conference on Digital System Design (DSD) (pp. 523-528). IEEE. [doi] [pdf]
  • Mentens, N., Miskovsky, V., Novotny, M., & Vliegen, J. (2018). High-speed Side-channel-protected Encryption and Authentication in Hardware. Cryptology ePrint Archive. [pdf]
  • Miškovský, V., Kubátová, H., & Novotný, M. (2018, June). Speeding up differential power analysis using integrated power traces. In 2018 7th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-5). IEEE. [doi] [pdf]
  • Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2018, August). Correlation Power Analysis Distinguisher Based on the Correlation Trace Derivative. In 2018 21st Euromicro Conference on Digital System Design (DSD) (pp. 565-568). IEEE Computer Soc. [doi] [pdf]

2017

  • Miškovský, V., Kubátová, H., & Novotný, M. (2017). Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA. Microprocessors and Microsystems, 51, 220-226. [doi] [pdf]
  • Říha, J., Miškovský, V., Kubátová, H., & Novotný, M. (2017, August). Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of Cryptographic Design. In 2017 Euromicro Conference on Digital System Design (DSD) (pp. 260-267). IEEE. [doi] [pdf]
  • Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2017, April). Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (pp. 184-189). IEEE. [doi] [pdf]

2016

  • Miškovský, V., Kubátová, H., & Novotný, M. (2016, June). Influence of fault-tolerant design methods on differential power analysis resistance of AES cipher: Methodics and challenges. In 2016 5th Mediterranean Conference on Embedded Computing (MECO) (pp. 14-17). IEEE. [doi] [pdf]