Petr Socha

Petr Socha
Position
PhD candidate
Research Interests
Hardware security, Side-channel analysis, FPGA design, Embedded systems
Email
petr.socha@fit.cvut.cz
Room
A-1051
Address

Thákurova 2077/7
Praha

Biography

Petr Socha received his master in embedded system design from Czech Technical University in Prague in 2019. Currently, Petr is a PhD student at the Faculty of Information Technology, Czech Technical University in Prague. His research interests include digital design, cryptographic hardware, and side-channel security.

  • PhD student, Faculty of Information Technology, CTU in Prague, 2019-now
  • Master's thesis "Software toolkit for side-channel attacks", 2019
  • Embedded Systems Design (graduate), Faculty of Information Technology, CTU in Prague, 2016-2018
  • Bachelor's thesis "Car dashboard model", 2016
  • Computer Engineering (undergraduate), Faculty of Information Technology, CTU in Prague, 2013-2016

Supervised theses

  • Tomáš Přeučil: Implementation of the signature scheme Rainbow on SoC FPGA, Master's thesis @ Uppsala University, 2021
  • David Pokorný: Side-channel analysis of Rainbow post-quantum signature, Master's thesis @ CTU in Prague, 2021

Publications

2021

  • Pokorný, D., Socha, P., & Novotný, M. (2021, February). Side-channel attack on Rainbow post-quantum signature. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 565-568). IEEE. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2021). High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation. Microprocessors and Microsystems, 85, 104311. [doi]

2020

  • Socha, P., & Novotný, M. (2020, August). Towards High-Level Synthesis of Polymorphic Side-Channel Countermeasures. In 2020 23rd Euromicro Conference on Digital System Design (DSD) (pp. 193-199). IEEE Computer Soc. [doi] [pdf]
  • Socha, P., Brejník, J., Balasch, J., Novotný, M., & Mentens, N. (2020). Side-channel countermeasures utilizing dynamic logic reconfiguration: Protecting AES/Rijndael and Serpent encryption in hardware. Microprocessors and Microsystems, 78, 103208. [doi]

2019

  • Socha, P., Brejník, J., Jeřábek, S., Novotný, M., & Mentens, N. (2019, August). Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent. In 2019 22nd Euromicro Conference on Digital System Design (DSD) (pp. 277-282). IEEE Computer Soc. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2019, June). First-Order and Higher-Order Power Analysis: Computational Approaches and Aspects. In 2019 8th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-5). IEEE. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2019, May) SICAK: An open-source SIde-Channel Analysis toolKit. In 2019 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE) [pdf]
  • Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2019). Efficient algorithmic evaluation of correlation power analysis: Key distinguisher based on the correlation trace derivative. Microprocessors and Microsystems, 71, 102858. [doi]

2018

  • Socha, P., Brejník, J., & Bartík, M. (2018, June). Attacking AES implementations using correlation power analysis on ZYBO Zynq-7000 SoC board. In 2018 7th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-4). IEEE. [doi] [pdf]
  • Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2018, August). Correlation Power Analysis Distinguisher Based on the Correlation Trace Derivative. In 2018 21st Euromicro Conference on Digital System Design (DSD) (pp. 565-568). IEEE Computer Soc. [doi] [pdf]

2017

  • Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2017, April). Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (pp. 184-189). IEEE. [doi] [pdf]