Petr Socha

Petr Socha
Position
Research scientist
Research Interests
Hardware security, Side-channel analysis, FPGA design, Embedded systems
E-mail
petr.socha@fit.cvut.cz
Room
A-1033
Address

Thákurova 2077/7
Praha

Biography

Petr Socha was born in Liberec, Czech Republic, in 1993. He received the Bachelor's degree in Computer Engineering and the Master's degree in Design and Programming of Embedded Systems from the Czech Technical University in Prague, Faculty of Information Technology, in 2016 and 2019, respectively.

He is a Research Scientist and a Ph.D. Candidate at the Czech Technical University in Prague. He is the author of 11 conference papers and three journal articles. His research interests include cryptographic hardware, side-channel security, embedded systems, and digital design. He teaches several university subjects and he also teaches IT at an elementary school. He is an external reviewer for the Microprocessors and Microsystems journal.

Mr. Socha's awards for his scientific work include the Stanislav Hanzl award (CTU in Prague, 2018) and the Josef Hlávka award (Hlávka Foundation, 2020). Mr. Socha is a member of the IEEE and IACR societies.

Supervised theses

  • Adam Rektořík: Effect of signal-to-noise ratio on the success of a side channel attack, Bachelor's thesis @ CTU in Prague, 2022
  • Tomáš Přeučil: Implementation of the signature scheme Rainbow on SoC FPGA, Master's thesis @ Uppsala University, 2021
  • David Pokorný: Side-channel analysis of Rainbow post-quantum signature, Master's thesis @ CTU in Prague, 2021

Publications

2022

  • Jedlicka, P., Malina, L., Socha, P., Gerlich, T., Martinasek, Z., & Hajny, J. (2022, August). On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography. In Proceedings of the 17th International Conference on Availability, Reliability and Security (pp. 1-9). [doi] [pdf]
  • Přeučil, T., Socha, P., & Novotný, M. (2022, August). Implementation of the Rainbow signature scheme on SoC FPGA. In 2022 25th Euromicro Conference on Digital System Design (DSD) (pp 513-519). IEEE Computer Soc. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2022, June). A fair experimental evaluation of distance correlation side-channel distinguisher. In 2022 11th Mediterranean Conference on Embedded Computing (MECO) (pp. 110-113). IEEE. [doi] [pdf]

2021

  • Pokorný, D., Socha, P., & Novotný, M. (2021, February). Side-channel attack on Rainbow post-quantum signature. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 565-568). IEEE. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2021). High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation. Microprocessors and Microsystems, 85, 104311. [doi]

2020

  • Socha, P., & Novotný, M. (2020, August). Towards High-Level Synthesis of Polymorphic Side-Channel Countermeasures. In 2020 23rd Euromicro Conference on Digital System Design (DSD) (pp. 193-199). IEEE Computer Soc. [doi] [pdf]
  • Socha, P., Brejník, J., Balasch, J., Novotný, M., & Mentens, N. (2020). Side-channel countermeasures utilizing dynamic logic reconfiguration: Protecting AES/Rijndael and Serpent encryption in hardware. Microprocessors and Microsystems, 78, 103208. [doi]

2019

  • Socha, P., Brejník, J., Jeřábek, S., Novotný, M., & Mentens, N. (2019, August). Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent. In 2019 22nd Euromicro Conference on Digital System Design (DSD) (pp. 277-282). IEEE Computer Soc. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2019, June). First-Order and Higher-Order Power Analysis: Computational Approaches and Aspects. In 2019 8th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-5). IEEE. [doi] [pdf]
  • Socha, P., Miškovský, V., & Novotný, M. (2019, May) SICAK: An open-source SIde-Channel Analysis toolKit. In 2019 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE) [pdf]
  • Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2019). Efficient algorithmic evaluation of correlation power analysis: Key distinguisher based on the correlation trace derivative. Microprocessors and Microsystems, 71, 102858. [doi]

2018

  • Socha, P., Brejník, J., & Bartík, M. (2018, June). Attacking AES implementations using correlation power analysis on ZYBO Zynq-7000 SoC board. In 2018 7th Mediterranean Conference on Embedded Computing (MECO) (pp. 1-4). IEEE. [doi] [pdf]
  • Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2018, August). Correlation Power Analysis Distinguisher Based on the Correlation Trace Derivative. In 2018 21st Euromicro Conference on Digital System Design (DSD) (pp. 565-568). IEEE Computer Soc. [doi] [pdf]

2017

  • Socha, P., Miškovský, V., Kubátová, H., & Novotný, M. (2017, April). Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (pp. 184-189). IEEE. [doi] [pdf]