Vít Mašek

Vít Mašek
Position
PhD student
Research Interests
Hardware security, Side-channel analysis, Post-Quantum Cryptography, ASIC & FPGA design
E-mail
masekvit@fit.cvut.cz
Room
A-1051
Address

Thákurova 2077/7
Praha

Publications

2025

  • Mašek, V., Miškovský, V. & Olekšák, M. (2025, September). Building a Side-Channel Attack Scheme on SipHash FPGA Implementation. In 2025 28th Euromicro Conference on Digital System Design (DSD) (pp. 160-164). IEEE Computer Soc. [doi] [pdf]
  • Mašek, V., Miškovský, V., & Olekšák, M. (2025, June). Building a Side-Channel Attack Scheme on SipHash FPGA Implementation. In Proceedings of the 13th Prague Embedded Systems Workshop (p. 28). CTU FIT, Department of Digital Design. [pdf]

2022

  • Mašek, V., & Novotný, M. (2022, April). Versatile Hardware Framework for Elliptic Curve Cryptography. In 2022 IEEE 25th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (pp. 80-83). IEEE. [doi] [pdf]